Next generation intelligence relies on advanced computing and sensing paradigms inspired mainly by the biological systems. However, today’s conventional cloud computing and mobile platforms have been already challenged by the advent of Artificial Intelligence (AI) and Internet of Things (IoT). The performance and diversity requirements of these applications demand the shift towards hyper-scale datacenters, Exascale high-performance computing (HPC), energy-efficient edge computing and connectivity, and new sensing and imaging modalities. Additionally, today’s existing biological techniques limit our understandings of complex biological systems such as human brain which is the main source of inspiration for shifting towards future computing and sensing paradigms. Our research goal is to design and implement large-scale and energy-efficient integrated systems that answer some of these major technological challenges by merging state-of-the-art electronics with photonics and other emerging technologies.
Our group focuses on all the crucial areas of integrated system design including: system-level modeling and architecture design, mixed-signal integrated circuits and systems, post-processing and integration technologies. The overarching principle of our integrated system methodology is based on enhancing and leveraging existing commercial CMOS technologies to unlock new functionalities and achieve unprecedented performances for new applications. Examples of such enhancements include: post-CMOS processing (fabrication steps after chips are fully fabricated at the foundry), 3D integration, re-purposing existing materials in standard CMOS processes (“zero-change” approaches), etc.
All-optical interrogation of cortical neurons enables simultaneous in-vivo readout and manipulation with single-neuron and single-action potential precision. This approach relies on Optogenetics and Calcium/Voltage imaging. In this work, both of these biological techniques will be miniaturized on a single implantable lens-less integrated system that can be wirelessly powered up and controlled. This system provides neural access to large areas of brain cortex bringing new opportunities to study brain circuits and building advanced brain-machine-interfaces.
Mental control of robots and machines by human brain can be a reality in near future. We are building a noninvasive high-bandwidth brain-computer-interface capable of recording/stimulating neurons in the visual cortex with high spatiotemporal resolution for this aim. In this project, a single photon avalanche diode (SPAD) based imager array will be implemented to record neural activity using Near-Infrared (NIR) optical tomography. Here is a press release on the end goal of this project on Neuroscience News.
We have demonstrated the first 40Gb/s optical PAM-4 transmitter in an “zero-change” (unmodified) 45nm SOI CMOS process. This transmitter achieves modulator and driver energy efficiency record of 42fJ/b which is 2 orders of magnitude more efficient than industry workhorse MZI-based transmitters In this work, we introduced an Optical DAC based on segmented microring modulator structures and a thermal tuning control loop for multi-level ring-resonator based transmitters. This high-speed Optical DAC can be also used for optical arbitrary waveform generators (AWG) and RF-photonics applications.
We have recently demonstrated the first dual-core processor SoC integrated with WDM optical I/Os. In this projects, we demonstrated an optical circuit switching network of these processor chips via a MEMS optical switch with microsecond switching time. This system demonstration is a promising solution to solve the electrical packet switching (EPS) scalability and energy-efficiency issue and enables novel architectures for emerging disaggregated and heterogeneous data-centers and HPC.
In order to realize the most energy-efficient and highest-bandwidth density interconnect across a range of applications, photonic devices need to be integrated as closely as possible to the most advanced transistors on a variety of chips designed mostly in a bulk CMOS process (e.g. processors, switches, memory chips, etc.). As a step toward creating a photonics process module that can be added to nanoscale CMOS process nodes, we demonstrated a polysilicon-based platform in a low-power 65nm bulk CMOS process in a 12” wafer foundry for the first time.
A monolithic photonic platform in an unmodified HKMG 32nm SOI CMOS process has been proposed in this work. This platform provides the fastest transistors monolithically integrated with photonic components. We showed high-speed O-band optical transceivers using resonant-based modulators and detectors with analog front-end circuits. Additionally, we exploited a new SiGe layer available in this process to improve the quantum-efficiency of resonant photo-detectors.
3D integration of electronics and photonics enables independent optimization of the photonic components and the CMOS circuits. We demonstrated for the first time a wafer-scale 3D electronic-photonic integrated platform, interfaced by the low capacitance (3fF/via) Through-Oxide-Vias (TOV) with 4μm pitch suitable for large-scale and energy-efficient electro-optical systems. This platform provides the densest 3D integration platform with the lowest parasitics among multi-wafer solutions.
Co-simulation and optimization of emerging integrated systems such as high-speed optical transceivers is a must to achieve the target performance and energy efficiency. This work proposes a new framework for designing high-speed silicon photonic transmitters by incorporating an accurate compact model for optical phase shifters, analytical models for photonic modulators and a new Simulink simulation toolbox. It allows us to explore the design trade-offs in depth for microring and Mach-Zehnder optical transmitters and compare their performances given the same set of technology and link constraints. Simulink Toolbox
As the number of photonic devices in advanced electro-optical systems such as LiDARs, optical switches, SoCs with optical I/O, quantum optics chips, and etc. are growing fast, the need for a “photonic VLSI flow” is imminent. We have developed a photonic layout versus schematic (PLVS) tool which extracts photonic devices and their properties from the layout and compares with the desired design parameters for the verification. It is compatible with original CMOS foundry PDKs and can recognize both PDK devices and new photonic structures. Our approach can be extended to other silicon photonics technologies with similar device structures as well.
